1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to circuitry for carrying out row selection internally at high speed in a special operation mode. More particularly, the present invention relates to a configuration for testing data retentionability of a memory cell in a dynamic semiconductor memory device.
2. Description of the Background Art
FIG. 37 schematically shows an entire structure of a conventional dynamic semiconductor memory device. This dynamic semiconductor memory device is a memory device in which the data in a memory cell is refreshed periodically. The dynamic semiconductor memory device can be any of a virtual static random access memory (VSRAM), a pseudo static random access memory (PSRAM), and a dynamic random access memory (DRAM). In FIG. 37, a structure of a dynamic random access memory is shown by way of example.
Referring to FIG. 37, the dynamic semiconductor memory device 1 includes a control circuit 6 receiving external control signals provided via external control signal input terminals (nodes) 2-5, i.e., a write enable signal /W, an output enable signal /OE, a row address strobe signal /RAS, and a column address strobe signal /CAS for generating an internal control signal, a memory array 7 with a plurality of dynamic type memory cells arranged in a matrix, an address buffer 9 receiving external address signal (bits) A0-Ai applied via address signal input terminals (nodes) 8 for generating an internal row address signal and an internal column address signal under control of control circuit 6, an internal address generation circuit 10 for generating a refresh row address signal that specifies a row to be refreshed in a refresh operation under control of control circuit 6, a multiplexer 11 for selectively and alternatively passing the address signals from address buffer 9 and internal address generation circuit 10 under control of control circuit 6, and a row decoder 12 activated under control of control circuit 6 for decoding an internal row address signal provided from multiplexer 11 to select an addressed row (word line) of memory array 7.
Signal /W instructs data writing when active (L level). Signal /OE instructs data output when active, to render an output buffer that will be described later operable. Row address strobe signal /RAS designates that an access to the semiconductor memory device is to be effected. Row address strobe signal /RAS initiates an internal operation of the DRAM and determines the active period of the internal operation. When row address strobe signal /RAS is active, circuitry related to the operation of selecting a row in memory array 7 (row related circuitry) such as row decoder 12 and the like is rendered active. Column address strobe signal /CAS renders circuitry related to selecting a column in memory array 7 active.
Semiconductor memory device 1 further includes a column decoder 13 activated, under control of control circuit 6, for decoding an internal column address signal from address buffer 9 to generate a column select signal to select a column in memory array 7, a sense amplifier for sensing and amplifying data of memory cells connected to a selected row in memory array 7, an IO gate responsive to the column select signal from column decoder 13 for connecting the selected column in memory array 7 to an internal data bus a1, an input buffer 15 for generating and transmitting to internal data bus a1 the internal write data from external write data DQ0-DQj provided to a data input/output terminal 17 in data writing, under control of control circuit 6, and an output buffer 16 for generating and providing to data input/output terminal 17 external read data DQ0-DQj from internal read data read out to internal data bus a1 in data reading, under control of control circuit 6. In FIG. 37, the sense amplifier and the IO gate are indicated as one block 14.
Input buffer 15 is activated when signals /W and /CAS both attain an active state of an L level to generate internal write data. Output buffer 16 is rendered active according to activation of output enable signal /OE.
FIG. 38 schematically shows an internal structure of memory array 7 shown in FIG. 37.
Referring to FIG. 38, memory array 7 includes a plurality of word lines WL arranged corresponding to respective rows of memory cells and having the memory cells of corresponding rows connected thereto, and a plurality of bit line pairs BL, /BL arranged corresponding to respective columns of memory cells and having the memory cells of corresponding columns connected thereto. In FIG. 38, word lines WL0, WL(l-1), word lines WLl and WL(l+1), and a pair of bit lines BL, /BL are representatively shown.
A memory cell is provided corresponding to a crossing of a pair of bit lines and a word line. In FIG. 38, a memory cell MCa arranged corresponding to the crossing of word line WL(l-1) and bit line /BL, a memory cell MCb arranged corresponding to the crossing between word line WLl and bit line BL, and a memory cell MCc arranged corresponding to the crossing of word line WL(l+1) and bit line /BL are representatively shown. Each of memory cells MCa-MCc includes a capacitor 23 storing information in the form of charges, and an access transistor 22 rendered conductive in response to a signal potential on a corresponding word line, for electrically connecting a corresponding bit line (BL or /BL) and capacitor 23. Access transistor 22 is formed of an n channel MOS (insulation gate field effect) transistor.
A row select signal from row decoder 12 is transmitted to word line WL (generically referring to WL0-WL(l+1)). The sense amplifier in block 14 includes a sense amplifier circuit arranged corresponding to a bit line pair BL, /BL for differentially amplifying the potential of the corresponding bit line pair BL and /BL. Row decoder 12 and the sense amplifier are sequentially rendered active according to activation of row address strobe signal /RAS. The operation of the semiconductor memory device of FIGS. 37 and 38 will be described with reference to the waveform diagram of FIG. 39. The operational waveform for data reading is shown by way of example in FIG. 39.
When row address strobe signal /RAS attains an inactive state of a high (H) level, semiconductor memory device 1 attains a standby state. Under this state, all the row select signals from row decoder 12 are in an inactive state, and the potential of word line WL is at a nonselected state of a low level. Bit lines BL and /BL are precharged to a predetermined potential (for example, Vcc/2:Vcc is an operating power supply voltage) by a precharge/equalize circuit not shown.
When row address strobe signal /RAS attains an active state of a low level, the memory cycle begins and a row select operation is initiated. Prior to initiation of this row select operation, the precharge operation of bit lines BL and /BL is ceased, whereby bit lines BL and /BL attain a floating state at the precharge potential.
Address buffer 9 responds to a control signal applied via a control signal bus a3 from control circuit 6 to take in external address signals A0-Ai provided via an address signal input terminals (node) 8 for providing an internal row address signal on an internal address bus a4. In FIG. 37, internal address bus a4 is shown having a width of (i+1) bits. However, address buffer 9 normally provides a pair of complementary address signals, so that the bit width of internal address bus a4 is 2.multidot.(i+1).
Multiplexer 11 selects and provides to row decoder 12 an internal row address signal provided from address buffer 9 under control of control circuit 6 in a normal operation mode in which data writing/reading is carried out. Row decoder 12 decodes the applied internal row address signal and provides a row select signal of an active state to the addressed word line in memory array 7. As a result, the potential of the selected word line WL is driven to a high level.
It is now assumed that word line WL1 is selected. Access transistor 22 of memory cell MCb is turned on, whereby capacitor 23 is connected to bit line BL. When memory cell MCb stores data of a high level, the potential of bit line BL slightly increases as shown in FIG. 39. In contrast, bit line /BL maintains the precharge potential since no memory cell is connected thereto. Then, the sense amplifier circuit in block 14 is activated to amplify the potential of bit lines BL and /BL differentially. The potential of bit line BL to which data of high level is read out increases to the level of the operating power supply voltage Vcc, whereas the potential of bit line /BL is discharged to the low (L) level of a ground potential.
When column address strobe signal /CAS attains an active state of a low level, address buffer 9 takes in internal address signals A0-Ai applied to address signal input terminals (node) 8 as a column address signal to generate an internal column address signal onto internal address bus a4 under control of control circuit 6. After the sense amplifier circuit is activated and the potential of bit lines BL and /BL is ascertained, column decoder 13 is rendered active under control of control circuit 6 to decode the internal column address signal from address buffer 9 to generate and output a column select signal.
In response to this column select signal, the IO gate (provided corresponding to each bit line pair) in block 14 is turned on, whereby the bit line pair provided corresponding to the column specified by the column select signal is connected to internal data bus a1 via the IO gate circuit rendered active. In reading out data, output enable signal /OE attains an active state of a low level. In response, output buffer 16 is rendered active under control of control circuit 6. External read data is generated from the internal read data on internal data bus a1. The generated external read data is transmitted to data input/output terminals 17. In data reading, write enable signal /W is maintained at an inactive state of a high level (indicated by the broken line in FIG. 39). In data writing, the timing of transmitting internal write data on internal data bus a1 is determined by the timing of signals /W and /CAS both being active.
Word lines WL are formed parallel to each other at the same interconnection layer, and are electrically isolated by an insulation film from each other. Therefore, parasitic capacitance is present between word lines as shown in FIG. 38. In FIG. 38, parasitic capacitance 25a between word lines WL(l-1) and WLl, and parasitic capacitance 25b between word lines WLl and WL(l+1) are representatively shown. This parasitic capacitance is present, not only between adjacent word lines, but also between remote word lines.
Bit lines BL and /BL and word line WL are formed in a direction crossing each other in different interconnection layers. Therefore, parasitic capacitance is present between a word line and a bit line at the crossing portion thereof via an interlayer insulation film. In FIG. 38, parasitic capacitance 26 between bit line BL and word line WL(l-1) is typically shown. The function of parasitic capacitances 25a and 25b, and 26 will now be described.
FIG. 40 shows in detail the distribution of the parasitic capacitances between word lines and between a word line and a bit line. Two word lines WLa and WLb, and a pair of bit lines BL and /BL are shown in FIG. 40. A memory cell MCd is provided corresponding to the crossing between bit line BL and word line WLa. A memory cell MCe is provided corresponding to the crossing between bit line /Bl and word line WLb. A constant reference voltage Vcp (generally, the voltage level of Vcc/2) is applied to one electrode of capacitor 23 in each of memory cells MCd and MCe.
There is parasitic capacitance 25c between word line WLa and word line WLb. There is parasitic capacitance 25d between word line WLa and a word line not shown. There is parasitic capacitance 25e between word line WLb and a word line not shown. There is parasitic capacitance 26a between word line WLa and bit line BL. There is parasitic capacitance 26b between bit line BL and word line WLb. Also, there are parasitic capacitances 26c and 26d between bit line /BL and word line WLa, and between bit line /BL and word line WLb, respectively.
The sense amplifier circuit provided corresponding to each respective bit line pair includes a P sense amplifier 27 activated in response to a sense amplifier activation signal .phi.SP to charge one of bit lines BL and /BL at the higher potential to the level of operating power supply voltage, and an N sense amplifier 28 activated in response to activation of a sense amplifier activation signal .phi.SN to discharge one of bit lines BL and /BL at the lower potential to the level of the ground potential.
The function of the parasitic capacitance of FIG. 4 will be described with reference to the operation waveform diagram of FIG. 41. FIG. 41 illustrates an operation when word line WLa is selected and memory cell MCd stores data of a high level (Vcc level).
When word line WLa is selected, the potential thereof increases. This potential increase of selected word line WLa is transmitted to word line WLb by the capacitive coupling through parasitic capacitance 25c. As a result, the potential of word line WLb slightly increases. FIG. 41 shows that the potential increase in nonselected word line WLb through the capacitive coupling causes ringing. This ringing is generated by the word driver provided corresponding to each word line in row decoder 12, maintaining the potential level of the nonselected word line at the low level of the ground voltage.
When the potential of selected word line WLa increases, access transistor 22 in memory cell MCd is turned on. The charge stored in capacitor 23 is transmitted to bit line BL. The potential of bit line BL is increased by .DELTA.R. When the read out voltage .DELTA.R on bit line BL attains a sufficient level, sense amplifier activation signals .phi.SN and .phi.SP are activated. In general, sense amplifier activation signal .phi.SN is first activated to enable N sense amplifier 28, whereby the potential of bit line /BL in a floating state at the level of precharge potential is discharged to the level of the ground potential. Then, sense amplifier activation signal .phi.SP is activated to enable P sense amplifier 27, whereby the potential of bit line BL is charged to the level of operating power supply voltage Vcc. The potential of nonselected word line WLb is raised by the capacitive coupling of parasitic capacitance 26b upon the potential increase of bit line BL. In operation of N sense amplifier 28, nonselected word line WLb is already at the level of the ground potential when the potential of bit line /BL is discharged to the level of the ground potential. In the case of the capacitive coupling between bit line /BL and nonselected word line WLb, the access transistor of nonselected memory cell MCe enters deeper off-state, and the waveform of the resultant undershooting is not illustrated since such a deep off-state is not particularly related to "disturb" that will be described later.
When one memory cycle is completed and the potential of selected word line WLa is driven from a high level to a low level, the potential of word line WLb is reduced via the capacitive coupling of parasitic capacitance 25c. Also, the potential of bit line /BL that has been discharged to the level of ground potential by N sense amplifier 28 is reduced via parasitic capacitance 26c.
The aforementioned potential floating-up of nonselected word line WLb will change the amount of charges stored in capacitor 23 of nonselected memory cell MCe as will be described in detail to alter the stored data in the memory cell. This problem of "disturb" will now be described with reference to FIGS. 42A-42C.
Referring to FIG. 42A, when the potential of nonselected word line WLb increases at the rise of the potential of selected word line WLa (point A in FIG. 41), access transistor 22 is slightly turned on to cause charge Q to flow from capacitor 23 to bit line /BL if data of a high level (Vcc) is stored in capacitor 23 of the memory cell connected to nonselected word line WLb. This rise .DELTA.V1 of nonselected word line WLb does not have to be greater than the threshold voltage of access transistor 22. Even when the potential of nonselected word line WLb increases approximately to the level of the threshold voltage of access transistor 22, charge Q flows from capacitor 23 to bit line /BL since the subthreshold current increases.
Referring to FIG. 42B, when P sense amplifier 27 operates and the potential of bit line BL is increased to cause the potential of nonselected word line WLb to rise by parasitic capacitance 26b, the potential of bit line /BL attains the level of ground potential Vss. Charge Q of a high level (Vcc level) stored in capacitor 23 of the memory cell flows towards bit line /BL.
Referring to FIG. 42C, when the potential of bit line /BL is reduced to the level of a negative potential -.DELTA.Vb by parasitic capacitance 26c of FIG. 40 (the parasitic capacitance between word line WLa and bit line /BL) at the transition of selected word line WLa to a nonselected state, charge Q of the high level data stored in capacitor 23 is discharged towards bit line /BL when the potential of nonselected word line WLb attains the level of ground potential Vss or negative potential -.DELTA.Va.
This flow of the stored charge occurs not only in data reading, but also in data writing. In other words, the charge flows out when the word line is selected or when the sense amplifier operates.
When data of a low level is stored in memory capacitor 23, the node connected to capacitor 23 functions as the source of the access transistor. The capacitance of memory capacitor 23 is sufficiently smaller than the capacitances of bit lines BL and /BL. Thus, the potential of memory capacitor 23 rises in response to only a small amount of charge flowing in, to make the potentials of the gate and source of access transistor 22 substantially equal to each other. As a result, the charge flow via the access transistor is ceased. Therefore, the increase of the amount of charge in memory capacitor 23 storing data of a low level will have its upper limit restricted.
When data of a high level is stored, charge flows out from a memory cell capacitor to a corresponding bit line to lower the potential of the memory cell capacitor every word line select operation, as shown in FIG. 43. In FIG. 43, the change in potential of word line WL(l) when word lines WL(l-1), WL(l+1), WL(l+2), . . . are sequentially selected is shown. In general, the memory cell capacitor has its capacitance value so set as to include a margin for charge leakage during operation. However, when the capacitance of the memory cell capacitor is reduced due to variation in the manufacturing parameters (film thickness of the capacitor insulation film, the facing area of capacitor electrodes, and the like), the potential of the storage node of the capacitor (the electrode node coupled to the bit line) is reduced in response to a slight flow out of charge. This causes the problem that the stored data is inverted.
Assuming that the capacitance value of memory cell 23 is C, and the stored charge amount is Q, the following equation can be obtained, provided that cell plate potential Vcp is Vcc/2. EQU Q=C.multidot.Vcc/2
Assuming that the leakage charge amount per charge leakage is .DELTA.Q, the change .DELTA.V of the electrode potential of the capacitor is obtained by the following equation. EQU .DELTA.Q=C.multidot..DELTA.V
Therefore, when the capacitance C of capacitor 23 becomes smaller, the potential change .DELTA.V becomes greater even when the flowing-out amount of charge .DELTA.Q is identical. Thus, the potential of the capacitor electrode of a defective cell that has a small capacitance is reduced more than the change in the capacitor electrode potential of a normal memory cell (indicated by broken line). The test to detect the presence of such a defective cell is called "disturb" test.
In this disturb test, a word line other than the word line that is connected to the memory cell of interest is selected for a predetermined number of times (number of disturbance times) to identify whether the data of the memory cell of interest is correctly retained or not. In such a disturb test, disturb testing is carried out simultaneously for a great number of semiconductor memory devices.
FIG. 44 schematically shows a structure for carrying out disturb testing. In FIG. 44, a plurality of semiconductor memory devices DR11-DRmn are mounted on a test board TB. FIG. 44 illustrates the case where semiconductor memory devices DR11-DRmn are arranged in m rows and n columns on test board TB. Semiconductor memory devices DR11-DRmn are connected to each other via a signal bus SG. Test board TB is connected to a tester TA. A signal necessary for the testing operation is applied from tester TA to signal bus SG. In the testing operation, semiconductor memory devices DR11-DRmn are simultaneously subjected to the disturb testing. First, data of a high level is written into semiconductor memory devices DR11-DRmn. Then, a row address strobe signal /RAS and an address signal are provided to signal bus SG from tester TA. A word line select operation and a sense amplifier circuit operation are carried out in semiconductor memory devices DR11-DRmn. By repeating this word line select operation for a predetermined number of times, word line WL connected to memory cells is affected by the noise, and charge leaks out from the memory cell capacitor. After selecting each word line and activating the sense amplifier circuit for a predetermined number of times, determination is made whether the data stored in semiconductor memory devices DR11-DRmn maintains the high level or not. This data determination operation is carried out by tester TA.
The number of word lines in a semiconductor memory device increases as the memory capacity becomes greater. Therefore, there is a problem that the disturb test of driving respective word lines sequentially into a selected state is time consuming. In order to reduce the testing time, an approach of altering row address strobe signal /RAS transmitted from tester TA to signal bus SG shown in FIG. 44 at high speed to reduce the selected time period of a word line can be conceived. However, a great number of semiconductor memory devices DR11-DRmn are connected to signal line SG, and there is a great parasitic capacitance Cp as shown in FIG. 44 at signal bus SG. Therefore, signal propagation is delayed due to the interconnection resistance and the great parasitic capacitance CP at signal bus SG. The required signal cannot be altered at high speed.
FIGS. 45A-45B show examples of the transition of row address strobe signal /RAS and an address signal on signal bus SG. FIG. 45 shows the ideal signal waveform on signal bus SG. FIG. 45B shows the signal waveform on signal bus SG in a conventional disturb test. As shown in FIG. 45A, row address strobe signal /RAS is altered at the predetermined rising time and falling time without the effect of the signal propagation delay. An address signal is required of a set up time Ts and a hold time Th with respect to signal /RAS. Set up time Ts is required to properly take in an address signal by holding the address signal at a definite state before the fall of signal /RAS. Hold time Th is required to reliably take in an address signal by maintaining the address signal at an definite state after signal /RAS falls.
When parasitic capacitance Cp of signal bus SG is great, the rising and falling times of row address strobe signal /RAS become longer due to the signal propagation delay on signal bus SG as shown in FIG. 45B. Therefore, the signal transition cannot be effected speedily. The transition speed of an address signal is similarly slowed down (address bus is similarly connected to semiconductor memory devices DR11-DRmn from tester TA). In order to ensure an address set up time Ts, the address signal must be altered at a timing faster than the address signal transition timing of the ideal waveform (FIG. 45A). Since the address signal is also altered when row address strobe signal /RAS attains a high level of an inactive state, the time period of the inactive state of row address strobe signal /RAS becomes longer than that of the ideal waveform. As a result, the time of one cycle (word line select cycle) of the disturb test becomes longer, and the word lines cannot sequentially be driven to a selected state at high speed, so that the disturb test time cannot be reduced.
The problem of not being able to drive word lines sequentially into a selected state speedily in the test operation is also encountered in an acceleration test such as the "burn-in" test. In this burn-in test, the semiconductor memory device is operated under the condition of a high temperature and a high voltage. Any potential initial defect such as gate insulation film defect or an interlayer insulation film defect between interconnections of an MOS transistor which is a constituent element, interconnection line fault, and defects caused by particles mixed during the fabrication process is made revealing to eliminate any faulty products before shipment. In the above acceleration test such as a burn-in test, only the operational conditions are modified in the semiconductor memory device. An operation similar to a normal mode operation is carried out according to a control signal provided from an external tester. Since the word lines are sequentially selected even in such an acceleration test, the problem of not being able to reduce the testing time is encountered. This problem is also encountered in life time testing and the like.
The specification values for the operating conditions and the like differ for each type (family) of the semiconductor memory device. A different design rule provides a different pitch of the word lines and a different capacitance value of the memory capacitor. Also, the degree of the rise of the word line potential and the amount of potential change of the memory capacitor differ in a different design rule. Therefore, the word line select cycle period (the period in which a word line is in a selected state) and the number of times where a word line is selected must be changed according to the type (family member) of the semiconductor memory device. This modification in the test condition requires that the program for operating the tester be modified, and the test condition cannot be modified flexibly and easily depending on the type of the semiconductor memory device to be tested.
A dynamic random access memory directed to carrying out word line selection speedily in a test operation is disclosed, for example, in Japanese Patent Laying-Open No. 5-342862. In this dynamic random access memory, an oscillator that oscillates at a cycle shorter than the self refresh cycle is activated in the test mode to drive a refresh address counter by an output signal from the oscillator. Word line selection/memory cell data refresh is carried out at a cycle shorter than the self refresh cycle to reduce the time required for the testing of whether the refresh counter operates properly or not. According to this prior art, only the oscillation cycle of the oscillator defining the self refresh cycle in the self refresh control circuit is modified. The refresh address is generated internally, and external designation of a select word line cannot be effected. The period of time in which the word line is maintained at a selected state is identical to that in a self refresh operation. This period of time cannot be modified. The degree of the potential rise of the nonselected word line is proportional to the period of time where the selected word line is placed in a selected state. This is because the amount of charge migration upon the capacitive coupling is proportional to the period of time where the selected word line is placed in a selected state. Therefore, although it is possible to determine whether the refresh counter operates properly in a short time, it is not possible to select a word line under various conditions to carry out disturb testing in the prior art. In this disturb testing, a word line select period cannot be controlled by an external signal.
An integrated circuit that can automatically carry out a test operation using an incorporated test circuit is disclosed in Japanese Patent Laying-Open No. 4-114400. In this prior art, a built-in oscillator is activated in a test mode. The incorporated test circuit is activated with the output signal of the oscillator as an internal row address strobe signal, to carry out testing. The oscillating cycle of this oscillator is constant, and the cycle cannot be modified from an external source. Also, the internal test is carried out autonomously inside the incorporated test circuit. It is not possible to externally identify which word line is driven to a selected state. Also, the time period of selecting a word line cannot be controlled by an external control signal.